1. Field of the Invention
The present invention is related to a nonvolatile memory device which is integrated by combining Static RAM (SRAM) cells and nonvolatile memory cells at a 1:1 ratio. In particular, it relates to a circuit for simply and accurately carrying out a recall from the novolatile memory cell to the static RAM cell.
2. Description of the Related Arts
A nonvolatile random access memory known as the nonvolatile RAM (NVRAM) is formed by integrating an Electrical Erasable PROM (EEPROM) and an SRAM on a basis of a ratio of 1:1 in the memory cell unit. In the NVRAM, the information stored in the SRAM can be stored in the EEPROM when the power source is turned off, and the information stored in the EEPROM can be recalled to the SRAM when the power source is turned on.
Conventionally, SRAM cells are formed by a flip-flop having depletion type transistors as loads, and a nonvolatile memory cell is formed by a transistor having a gate in a floating state, for example, a transistor having a floating-gate tunnel oxide (FLOTOX) structure, described later.
In the conventional nonvolatile RAM, as explained in detail hereinafter, the pair of transistors is formed in such a manner that the state of the flip-flop becomes unbalanced. This unbalanced state is formed by the load transistor or by adding capacitors.
However, because the pair of transistors or the pair of capacitors are in an unbalanced state, the relationship between a low level and a high level in flip-flop becomes unsymmetrical and the access speed is reduced. Further, a problem arises in that, as the unbalance between the transistors requires a corresponding unbalance of the cell current, then the an increase of dissipation current occurs. Further, because a depletion type MOS transistor is used as a flip-flop load in the static memory portion, the drawback of an increase in the electric power dissipation arises. Further, the unbalanced state as mentioned above increases the cell area, and the integration density is decreased.